The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 10, 2022
Filed:
Dec. 14, 2020
International Business Machines Corporation, Armonk, NY (US);
Steven J. Battle, Philadelphia, PA (US);
Kurt A. Feiste, Austin, TX (US);
Susan E. Eisen, Round Rock, TX (US);
Dung Q. Nguyen, Austin, TX (US);
Christian Gerhard Zoellin, Austin, TX (US);
Kent Li, Austin, TX (US);
Brian W. Thompto, Austin, TX (US);
Dhivya Jeganathan, Austin, TX (US);
Kenneth L. Ward, Austin, TX (US);
Brian D. Barrick, Pflugerville, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
In at least one embodiment, a processor includes architected and non-architected register files for buffering operands. The processor additionally includes an instruction fetch unit that fetches instructions to be executed and at least one execution unit. The at least one execution unit is configured to execute a first class of instructions that access operands in the architected register file and a second class of instructions that access operands in the non-architected register file. The processor also includes a mapper circuit that assigns physical registers to the instructions for buffering of operands. The processor additionally includes a dispatch circuit configured, based on detection of an instruction in one of the first and second classes of instructions for which correct operands do not reside in a respective one of the architected and non-architected register files, to automatically initiate transfer of operands between the architected and non-architected register files.