The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 03, 2022
Filed:
May. 17, 2019
Applicant:
Citrix Systems, Inc., Fort Lauderdale, FL (US);
Inventors:
Jeremy White, Fort Lauderdale, FL (US);
Shawn Edmondson, Raleigh, NC (US);
Chiradeep Vittal, Santa Clara, CA (US);
Assignee:
CITRIX SYSTEMS, INC., Fort Lauderdale, FL (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 12/26 (2006.01); H04L 12/911 (2013.01); H04L 43/0823 (2022.01); H04L 43/04 (2022.01); H04L 43/0876 (2022.01); H04L 47/70 (2022.01);
U.S. Cl.
CPC ...
H04L 43/0823 (2013.01); H04L 43/04 (2013.01); H04L 43/0876 (2013.01); H04L 47/822 (2013.01);
Abstract
The disclosure is directed towards systems and methods for injecting or introducing synthetic errors and latency for testing purposes into microservices provided by one or more servers. A device acting as an intermediary to communication can inject errors into responses or requests traversing the device. The errors can include additional latency, dropped packets, or memory or disk errors. Introducing errors and latency for testing purposes can be used to proactively monitor and identify issues with resources.