The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 03, 2022

Filed:

Nov. 30, 2020
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Bob W. Verbruggen, Dublin, IE;

Christophe Erdmann, Dublin, IE;

Ionut C. Cical, Dublin, IE;

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 25/02 (2006.01); H03K 5/133 (2014.01); H03K 3/037 (2006.01); H05K 1/02 (2006.01); G06F 13/40 (2006.01);
U.S. Cl.
CPC ...
H03K 5/133 (2013.01); G06F 13/4086 (2013.01); H03K 3/037 (2013.01); H04L 25/0298 (2013.01); H05K 1/0246 (2013.01);
Abstract

A low current line termination circuit includes first and second input interfaces each configured to receive a Vreceive+ and a Vreceive− voltage, respectively. The circuit further includes a first diode connected transistor ('DCT') coupled to the second input interface, a first switching transistor ('ST') coupled to the first DCT and to the first input interface, and a first delay element coupled between one of the input interfaces and a gate of the first ST. The circuit further includes a second DCT coupled to the one of the two input interfaces, a second ST coupled to the second DCT and to the second input interface, and a second delay element coupled between another of the two input interfaces and a gate of the second ST.


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