The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 03, 2022

Filed:

Oct. 23, 2020
Applicant:

Murata Manufacturing Co., Ltd., Kyoto, JP;

Inventors:

Satoshi Arayashiki, Kyoto, JP;

Kazuo Watanabe, Kyoto, JP;

Satoshi Tanaka, Kyoto, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 3/45 (2006.01); H03F 3/21 (2006.01); H03F 1/02 (2006.01); H03F 3/30 (2006.01);
U.S. Cl.
CPC ...
H03F 3/211 (2013.01); H03F 1/0211 (2013.01); H03F 3/45089 (2013.01); H03F 3/3022 (2013.01); H03F 3/45085 (2013.01); H03F 3/45183 (2013.01); H03F 2200/102 (2013.01); H03F 2200/21 (2013.01); H03F 2200/267 (2013.01); H03F 2200/451 (2013.01); H03F 2203/21106 (2013.01); H03F 2203/21142 (2013.01); H03F 2203/45138 (2013.01); H03F 2203/45296 (2013.01); H03F 2203/45316 (2013.01);
Abstract

A power amplifier circuit includes lower-stage and upper-stage differential amplifying pairs, a combiner, first and second inductors, and first and second capacitors. First and second signals are input into the lower-stage differential amplifying pair. The upper-stage differential amplifying pair outputs first and second amplified signals. The combiner combines the first and second amplified signals. The lower-stage differential amplifying pair includes first and second transistors. A supply voltage is supplied to the collectors of the first and second transistors. The first and second signals are supplied to the bases of the first and second transistors. The upper-stage differential amplifying pair includes third and fourth transistors. A supply voltage is supplied to the collectors of the third and fourth transistors. The emitters of the third and fourth transistors are grounded via the first and second inductors and are connected to the first and second transistors via the first and second capacitors.


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