The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 03, 2022

Filed:

Apr. 27, 2018
Applicant:

Hewlett Packard Enterprise Development Lp, Houston, TX (US);

Inventors:

Amit S. Sharma, Milpitas, CA (US);

John Paul Strachan, Milpitas, CA (US);

Martin Foltin, Fort Collins, CO (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 27/24 (2006.01); H01L 29/161 (2006.01); H01L 29/808 (2006.01);
U.S. Cl.
CPC ...
H01L 27/2454 (2013.01); H01L 21/02532 (2013.01); H01L 27/2463 (2013.01); H01L 29/161 (2013.01); H01L 29/66909 (2013.01); H01L 29/8083 (2013.01);
Abstract

Devices and methods are provided. In one aspect, a device for driving a memristor array includes a substrate including a well having a bottom layer, a first wall and a second wall. The substrate is formed of a strained layer of a first semiconductor material. A vertical JFET is formed in the well. The vertical JFET includes a vertical gate region formed in a middle portion of the well with a gate region height less than a depth of the well. A channel region is formed of an epitaxial layer of a second semiconductor wrapped around the vertical gate region. Vertical source regions are formed on both sides of a first end of the vertical gate region, and vertical drain regions are formed on both sides of a second end of the vertical gate region.


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