The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 03, 2022

Filed:

Aug. 24, 2020
Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventors:

Ashish Baraskar, Santa Clara, CA (US);

Raghuveer S. Makala, Campbell, CA (US);

Peter Rabkin, Cupertino, CA (US);

Assignee:

SANDISK TECHNOLOGIES LLC, Addison, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11556 (2017.01); H01L 27/11524 (2017.01); H01L 21/8239 (2006.01); H01L 27/11582 (2017.01); H01L 27/1157 (2017.01); H01L 21/8234 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11556 (2013.01); H01L 21/8239 (2013.01); H01L 21/823418 (2013.01); H01L 21/823487 (2013.01); H01L 27/1157 (2013.01); H01L 27/11524 (2013.01); H01L 27/11582 (2013.01); H01L 29/0847 (2013.01); H01L 29/1037 (2013.01);
Abstract

A memory device includes a silicon-germanium source contact layer, an alternating stack of insulating layers and electrically conductive layers located over the silicon-germanium source contact layer, and a memory stack structure vertically extending through the alternating stack. The memory stack structure comprises a memory film and a vertical semiconductor channel that contacts the memory film. The silicon-germanium source contact layer contacts a cylindrical portion of an outer sidewall of the vertical semiconductor channel. Logic circuits for operating the memory elements may be provided on a substrate within a same semiconductor die, or may be provided in another semiconductor die that is bonded to the semiconductor die containing the memory device.


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