The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 03, 2022
Filed:
Jan. 05, 2021
Applicant:
Stmicroelectronics (Rousset) Sas, Rousset, FR;
Inventors:
Pascal Fornara, Pourrieres, FR;
Fabrice Marinet, Chateauneuf le Rouge, FR;
Assignee:
STMicroelectronics (Rousset) SAS, Rousset, FR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 17/16 (2006.01); H01L 27/112 (2006.01); H01L 23/58 (2006.01); H01L 23/528 (2006.01); G11C 17/18 (2006.01); H01L 23/525 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11206 (2013.01); G11C 17/16 (2013.01); G11C 17/18 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 23/5252 (2013.01); H01L 23/585 (2013.01);
Abstract
An integrated circuit includes a memory cell incorporating an antifuse device. The antifuse device includes a state transistor having a control gate and a second gate that is configured to be floating. A dielectric layer between the control gate and the second gate is selectively blown in order to confer a broken-down state on the antifuse device where the second gate is electrically coupled to the control gate for storing a first logic state. Otherwise, the antifuse device is in a non-broken-down state for storing a second logic state.