The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 03, 2022

Filed:

Jan. 23, 2018
Applicant:

Mitsubishi Electric Corporation, Tokyo, JP;

Inventors:

Hodaka Rokubuichi, Tokyo, JP;

Kuniyuki Sato, Tokyo, JP;

Kiyofumi Kitai, Tokyo, JP;

Yasuyuki Sanda, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 23/4952 (2013.01); H01L 21/565 (2013.01); H01L 23/3121 (2013.01); H01L 23/49575 (2013.01);
Abstract

A semiconductor device and a semiconductor module which can be reduced in size while ensuing insulation are provided. In the semiconductor device, a lead frame on which a circuit pattern is formed is provided on an insulation substrate; the circuit pattern of the lead frame is joined to the back-side electrode of a semiconductor chip via a solder layer, and the lead frame is electrically connected with the top-side electrode of the semiconductor chip via a wire; the lead frameincludes a terminal inside a mold-sealing resin and a terminal exposed to a space outside the mold-sealing resin, and the terminal is connected to a terminal block via a solder layer; and the lead frame, the insulation substrate, the semiconductor chip and the terminal block are integrally molded and sealed by the mold-sealing resin.


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