The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 03, 2022

Filed:

Aug. 20, 2020
Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Inventors:

Mitsuo Sano, Kamakura, JP;

Susumu Obata, Yokohama, JP;

Kazuhito Higuchi, Yokohama, JP;

Kazuo Shimokawa, Yokohama, JP;

Assignee:

KABUSHIKI KAISHA TOSHIBA, Minato-ku, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01G 4/33 (2006.01); H01G 4/01 (2006.01); H01G 4/012 (2006.01); H01G 4/30 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01G 4/33 (2013.01); H01G 4/01 (2013.01); H01G 4/012 (2013.01); H01G 4/306 (2013.01); H01L 28/90 (2013.01);
Abstract

According to an embodiment, a capacitor includes a conductive substrate, a conductive layer and a dielectric layer. The conductive substrate has a first main surface and a second main surface. The first main surface includes sub-regions. Each sub-region is provided with recesses or projections each having a shape extending in one direction and arranged in a width direction thereof. One or more of the sub-regions and another one or more of the sub-regions are different from each other in a length direction of the recesses or protrusions. The conductive layer covers sidewalls and bottom surfaces of the recesses or sidewalls and top surfaces of the projections. The dielectric layer is interposed between the conductive substrate and the conductive layer.


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