The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 03, 2022

Filed:

Aug. 30, 2019
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventor:

Taira Shibuya, Fujisawa Kanagawa, JP;

Assignee:

KIOXIA CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/24 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01);
U.S. Cl.
CPC ...
G11C 16/10 (2013.01); G11C 16/0466 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); G11C 16/3436 (2013.01); G11C 16/0483 (2013.01);
Abstract

A semiconductor memory device includes first and second memory cells, adjacent first and second word line connected to gates of the first and second memory cells, respectively, a word line driver for the first and second word lines, a bit line connected to the first and second memory cells, a sense amplifier circuit configured to detect data stored in the memory cells via the bit line and apply a voltage to the bit line, and a control circuit configured to control the word line driver and the sense amplifier circuit to execute a write operation. During a write operation performed on the first memory cell to increase a threshold voltage of the first memory cell to a target state, the control circuit changes the bit line voltage of the bit line according to a difference between the target state and a threshold voltage state of the second memory cell.


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