The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 03, 2022

Filed:

Jan. 19, 2018
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Takeo Yasuda, Nara, JP;

Masatoshi Ishii, Yokohama, JP;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06N 3/063 (2006.01); G06N 3/04 (2006.01); G11C 15/04 (2006.01); G06N 3/08 (2006.01); G06N 3/10 (2006.01); G11C 13/00 (2006.01); G06N 3/00 (2006.01); G11C 8/16 (2006.01); G11C 11/56 (2006.01); G11C 11/54 (2006.01);
U.S. Cl.
CPC ...
G06N 3/0635 (2013.01); G06N 3/00 (2013.01); G06N 3/049 (2013.01); G06N 3/08 (2013.01); G06N 3/10 (2013.01); G11C 8/16 (2013.01); G11C 11/54 (2013.01); G11C 11/56 (2013.01); G11C 13/004 (2013.01); G11C 13/0023 (2013.01); G11C 13/0061 (2013.01); G11C 13/0069 (2013.01); G11C 15/046 (2013.01); G11C 2013/0088 (2013.01);
Abstract

A synapse memory system includes: synapse memory cells provided at cross points of axon lines and dendrite lines, each synapse memory cell being associated with nonvolatile random-access memory (NVRAM), each synapse memory cell being configured to store a weight value according to an output level of a write signal; a write portion configured to write the weight value to each synapse memory cell, the write portion including a write driver and an output controller, the write driver being a digital driver configured to output the write signal to a subject synapse memory cell, the output controller being configured to control the output level of the write signal of the write driver; and read drivers configured to read the weight value stored in the synapse memory cells.


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