The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 03, 2022

Filed:

Aug. 31, 2020
Applicant:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Inventors:

Jagadish B. Kotra, Austin, TX (US);

Michael W. LeBeane, Austin, TX (US);

Assignee:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/1027 (2016.01); G06F 12/0862 (2016.01); G06F 12/0891 (2016.01); G06F 12/126 (2016.01); G06F 12/0846 (2016.01);
U.S. Cl.
CPC ...
G06F 12/1027 (2013.01); G06F 12/0848 (2013.01); G06F 12/0862 (2013.01); G06F 12/0891 (2013.01); G06F 12/126 (2013.01); G06F 2212/1021 (2013.01);
Abstract

Techniques are disclosed for processing address translations. The techniques include detecting a first miss for a first address translation request for a first address translation in a first translation lookaside buffer, in response to the first miss, fetching the first address translation into the first translation lookaside buffer and evicting a second address translation from the translation lookaside buffer into an instruction cache or local data share memory, detecting a second miss for a second address translation request referencing the second address translation, in the first translation lookaside buffer, and in response to the second miss, fetching the second address translation from the instruction cache or the local data share memory.


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