The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 03, 2022

Filed:

Dec. 28, 2021
Applicant:

Aistartek HK Limited, Hong Kong, CN;

Inventors:

Zhongxuan Zhang, San Diego, CA (US);

Yucong Gu, San Jose, CA (US);

Assignee:

Other;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/523 (2006.01); G06N 3/063 (2006.01); G11C 11/412 (2006.01); H03M 1/12 (2006.01);
U.S. Cl.
CPC ...
G06F 7/523 (2013.01); G06N 3/0635 (2013.01); G11C 11/412 (2013.01); H03M 1/12 (2013.01);
Abstract

A system for analog computing, an analog computing system with sub-binary radix weight representation is provided. The analog computing system comprises an input node, a multiplexer (MUX), a digital to analog converter (DAC), a SRAM-based Sub-Binary Multiplier (SSBM), an analog to digital converter (ADC), a switch, an output node and a calibration module. The calibration module is configured to control the analog computing system to switch between a calibration mode and a normal operation mode. Prior to being switched to the normal operation mode, the analog computing system is configured to perform a process to calibrate a weight parameter stored in the SSBM. The ADC comprises a plurality of multipliers associated with a plurality of sub-binary weight radixes. The weight parameter stored in the SSBM and the plurality of sub-binary weight radixes are configured to represent a plurality of weights for the analog computing system.


Find Patent Forward Citations

Loading…