The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 26, 2022
Filed:
Aug. 24, 2020
Applicant:
Powerchip Semiconductor Manufacturing Corporation, Hsinchu, TW;
Inventors:
Assignee:
Powerchip Semiconductor Manufacturing Corporation, Hsinchu, TW;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/739 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/10 (2006.01); H01L 29/40 (2006.01); H01L 29/423 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7393 (2013.01); H01L 29/063 (2013.01); H01L 29/0653 (2013.01); H01L 29/0847 (2013.01); H01L 29/1095 (2013.01); H01L 29/402 (2013.01); H01L 29/4236 (2013.01); H01L 29/66325 (2013.01);
Abstract
An insulated gate bipolar transistor (IGBT) structure including a substrate and a first gated PNPN diode is provided. The first gated PNPN diode is located on the substrate. The first gated PNPN diode includes a first gate, a first source/drain extension (SDE) region, and a second SDE region. The first gate is located on the substrate. The first SDE region and the second SDE region are located in the substrate on two sides of the first gate.
Chen, Chun-Sheng. (2022). Insulated gate bipolar transistor structure and manufacturing method thereof (U.S. Patent No. 11316036). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11316036
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile