The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 26, 2022

Filed:

Nov. 11, 2020
Applicant:

Electronics and Telecommunications Research Institute, Daejeon, KR;

Inventors:

Sung-Jae Chang, Daejeon, KR;

Dong Min Kang, Daejeon, KR;

Sung-Bum Bae, Daejeon, KR;

Hyung Sup Yoon, Daejeon, KR;

Kyu Jun Cho, Daejeon, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 21/84 (2006.01); H01L 21/683 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 27/12 (2013.01); H01L 21/6835 (2013.01); H01L 21/84 (2013.01); H01L 23/3171 (2013.01); H01L 2221/6835 (2013.01); H01L 2221/68318 (2013.01);
Abstract

Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes a substrate having a first region and a second region, a buffer layer disposed on the substrate, a semiconductor layer disposed on the buffer layer, a barrier layer disposed on the semiconductor layer, a first source electrode, a first drain electrode, and a first gate electrode disposed therebetween, which are disposed on the barrier layer in the first region, a second source electrode, a second drain electrode, and a second gate electrode disposed therebetween, which are disposed on the barrier layer in the second region, and a ferroelectric pattern interposed between the first gate electrode and the barrier layer.


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