The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 26, 2022

Filed:

Sep. 15, 2020
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventors:

Toshifumi Minami, Yokohama Kanagawa, JP;

Atsuhiro Sato, Meguro Tokyo, JP;

Keisuke Yonehama, Kamakura Kanagawa, JP;

Yasuyuki Baba, Zama Kanagawa, JP;

Hiroshi Shinohara, Yokosuka Kanawaga, JP;

Hideyuki Kamata, Kawasaki Kanagawa, JP;

Teppei Higashitsuji, Fujisawa Kanagawa, JP;

Assignee:

KIOXIA CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 27/11565 (2017.01); H01L 27/1157 (2017.01); H01L 27/11578 (2017.01); H01L 27/11551 (2017.01); H01L 27/11563 (2017.01); H01L 27/11556 (2017.01); H01L 29/792 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 27/1157 (2013.01); H01L 27/11551 (2013.01); H01L 27/11556 (2013.01); H01L 27/11563 (2013.01); H01L 27/11565 (2013.01); H01L 27/11578 (2013.01); H01L 29/7926 (2013.01);
Abstract

A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.


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