The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 26, 2022
Filed:
Mar. 05, 2020
Semiconductor memory device having three-dimensional structure and method for manufacturing the same
Applicant:
SK Hynix Inc., Icheon-si, KR;
Inventors:
Tae Sung Park, Icheon-si, KR;
Sung Lae Oh, Cheongju-si, KR;
Dong Hyuk Kim, Seoul, KR;
Soo Nam Jung, Seoul, KR;
Assignee:
SK hynix Inc., Icheon-si, KR;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/11 (2006.01); H01L 27/11582 (2017.01); H01L 27/11551 (2017.01); H01L 27/108 (2006.01); H01L 27/11543 (2017.01); H01L 27/112 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1116 (2013.01); H01L 27/10835 (2013.01); H01L 27/11273 (2013.01); H01L 27/11543 (2013.01); H01L 27/11551 (2013.01); H01L 27/11582 (2013.01);
Abstract
A semiconductor memory device includes a stack disposed over a first substrate; an etch barrier including a plurality of dummy channels which pass through the stack and surround a coupling region; and a plurality of channels passing through the stack in a cell region outside the coupling region. The stack has a structure in which first dielectric layers and second dielectric layers are alternately stacked, inside the coupling region, and has a structure in which the first dielectric layers and electrode layers are alternately stacked, outside the coupling region.