The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 26, 2022

Filed:

Mar. 03, 2017
Applicant:

Hewlett Packard Enterprise Development Lp, Houston, TX (US);

Inventors:

Brent Buchanan, Palo Alto, CA (US);

Miao Hu, Palo Alto, CA (US);

John Paul Strachan, Palo Alto, CA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06N 3/063 (2006.01); G11C 13/00 (2006.01); H03M 1/12 (2006.01); G06F 7/544 (2006.01);
U.S. Cl.
CPC ...
G06N 3/0635 (2013.01); G06F 7/5443 (2013.01); G11C 13/0069 (2013.01); H03M 1/1245 (2013.01); G06F 2207/4802 (2013.01); G06F 2207/4824 (2013.01);
Abstract

An example electronic device includes a crossbar array, row driver circuitry, and column output circuits for each of the column lines of the crossbar array. The crossbar array may include row lines, column lines, and memristors that each are connected between one of the row lines and one of the column lines. The row driver circuitry may be to apply a plurality of analog voltages to a first node during a plurality of time periods, respectively, and, for each of the row lines, selectively connect the row line to the first node during one of the plurality of time periods based on a digital input vector. The column output circuits may each include: an integration capacitor, a switch that is controlled by an integration control signal, and current mirroring circuitry. The current mirroring circuitry may be to, when the switch is closed, flow an integration current to or from an electrode of the integration capacitor whose magnitude mirrors a current flowing on the corresponding column line. The integration control signal may be to close the switch for a specified amount of time during each of the plurality of time periods.


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