The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 26, 2022

Filed:

Oct. 09, 2020
Applicant:

Raytheon Company, Waltham, MA (US);

Inventors:

Hrishikesh Shinde, Dallas, TX (US);

Daryl Coleman, McKinney, TX (US);

Assignee:

Raytheon Company, Waltham, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/42 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4204 (2013.01); G06F 13/4282 (2013.01); G06F 2213/0002 (2013.01); G06F 2213/0004 (2013.01);
Abstract

Methods and apparatus for implementing a bus in a resource constrained system. In embodiments, a first FPGA is to a parallel bus and a second FPGA is connected to the first FPGA via a serial interface but not the parallel bus. The first FPGA processes a transaction request, which has a parallel bus protocol format, to the second FPGA by an initiator and converts the transaction request to the second FPGA into a transaction on the serial interface between the first and second FPGAs. The first FPGA responds to the initiator via the parallel bus indicating that the transaction request in the format for the parallel bus to the second FPGA is complete.


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