The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 26, 2022

Filed:

Jan. 29, 2021
Applicant:

Liqid Inc., Broomfield, CO (US);

Inventors:

James Scott Cannata, Denver, CO (US);

German Kazakov, Longmont, CO (US);

Christopher R. Long, Colorado Springs, CO (US);

Jason Breakstone, Broomfield, CO (US);

Assignee:

Liqid Inc., Broomfield, CO (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/50 (2006.01); G06F 13/40 (2006.01); G06T 1/20 (2006.01); G06F 13/42 (2006.01); G06F 12/02 (2006.01); G06F 13/28 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4022 (2013.01); G06F 9/5044 (2013.01); G06F 9/5077 (2013.01); G06F 12/02 (2013.01); G06F 13/28 (2013.01); G06F 13/4282 (2013.01); G06T 1/20 (2013.01); G06F 2213/0026 (2013.01);
Abstract

Disaggregated computing architectures, platforms, and systems are provided herein. In one example, a method includes receiving user input to establish a compute unit comprising a host processor and at least two graphics processing units (GPUs) having a peer-to-peer capability. The method also includes instructing a management element for a communication fabric to form the compute unit and communicatively couple the host processor and the at least two GPUs over the communication fabric. The method also includes instructing the management element to establish an isolation function to form the peer arrangement between the at least two GPUs in the communication fabric, where the isolation function isolates a first address domain associated with the at least two GPUs from at least a second address domain associated with the host processor by at least establishing synthetic devices representing the at least two GPUs in the second address domain.


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