The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 26, 2022

Filed:

Sep. 18, 2020
Applicant:

Dell Products, Lp, Round Rock, TX (US);

Inventors:

Dor Aharony, Newton, MA (US);

Stephen Strickland, Foxborough, MA (US);

Gary W. Smith, Cumberland, RI (US);

Assignee:

Dell Products, LP, Round Rock, TX (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/16 (2006.01); G06F 13/42 (2006.01); G06F 1/10 (2006.01); G06F 1/20 (2006.01); G06F 1/18 (2006.01); G06F 1/16 (2006.01); G06F 1/04 (2006.01);
U.S. Cl.
CPC ...
G06F 13/1668 (2013.01); G06F 1/04 (2013.01); G06F 1/10 (2013.01); G06F 1/1658 (2013.01); G06F 1/187 (2013.01); G06F 1/206 (2013.01); G06F 13/4291 (2013.01); G06F 2213/0026 (2013.01);
Abstract

A non-volatile memory express (NVMe) based storage system may include a processor; an input/output (I/O) port operatively coupled to a data network; a drive interface board (DIB), including: a PCIe switch communicatively coupled to the processor to receive signals from the processor to a plurality of NVMe storage devices; and a source clock communicatively coupled to the PCIe switch; a connector communicatively coupling the DIB to relay clock signals to a plurality of NVMe drives at a drive mid-plane baseboard; the drive mid-plane baseboard communicatively coupled to the source clock, the drive mid-plane baseboard including: a clock distribution module to receive a source clock signal from the source clock, the clock distribution modules placed at the drive baseboard to distribute the clock signals to the plurality of NVMe storage devices.


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