The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 19, 2022

Filed:

Sep. 26, 2019
Applicant:

Panasonic Intellectual Property Management Co., Ltd., Osaka, JP;

Inventors:

Daisuke Ikeda, Toyama, JP;

Gen Shimizu, Toyama, JP;

Hideo Kitagawa, Toyama, JP;

Toru Takayama, Koyama, JP;

Masayuki Ono, Koyama, JP;

Katsuya Samonji, Toyama, JP;

Osamu Tomita, Osaka, JP;

Satoko Kawasaki, Osaka, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01S 5/343 (2006.01); H01S 5/026 (2006.01); H01S 5/02 (2006.01); H01S 5/22 (2006.01); H01L 21/20 (2006.01); H01L 21/3065 (2006.01); B28D 5/00 (2006.01); H01L 33/00 (2010.01); H01L 21/285 (2006.01);
U.S. Cl.
CPC ...
H01S 5/34333 (2013.01); B28D 5/0011 (2013.01); B28D 5/0023 (2013.01); H01L 21/20 (2013.01); H01L 21/3065 (2013.01); H01L 33/0075 (2013.01); H01S 5/0202 (2013.01); H01S 5/026 (2013.01); H01S 5/2202 (2013.01); H01S 5/34346 (2013.01); H01L 21/28512 (2013.01); H01S 2304/00 (2013.01);
Abstract

In a method for manufacturing a nitride semiconductor light-emitting element by splitting a semiconductor layer stacked substrate including a semiconductor layer stacked body with a plurality of waveguides extending along the Y-axis to fabricate a bar-shaped substrate, and splitting the bar-shaped substrate along a lengthwise split line to fabricate an individual element, the waveguide in the individual element has different widths at one end portion and the other end portion and the center line of the waveguide is located off the center of the individual element along the X-axis, and in the semiconductor layer stacked substrate including a first element forming region and a second element forming region which are adjacent to each other along the X-axis, two lengthwise split lines sandwiching the first element forming region and two lengthwise split lines sandwiching the second element forming region are misaligned along the X-axis.


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