The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 19, 2022

Filed:

Apr. 19, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

John Collins, Tarrytown, NY (US);

Ali Afzali-Ardakani, Ossining, NY (US);

Teodor K. Todorov, Yorktown Heights, NY (US);

Joel P. de Souza, Putnam Valley, NY (US);

Devendra K. Sadana, Pleasantville, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01M 10/39 (2006.01); H01M 10/0562 (2010.01); H01M 10/0525 (2010.01); H01M 4/137 (2010.01); H01M 4/1399 (2010.01); H01M 4/1395 (2010.01); H01M 4/38 (2006.01); H01M 4/131 (2010.01); H01M 4/134 (2010.01); H01M 4/36 (2006.01);
U.S. Cl.
CPC ...
H01M 10/399 (2013.01); H01M 4/131 (2013.01); H01M 4/134 (2013.01); H01M 4/137 (2013.01); H01M 4/1395 (2013.01); H01M 4/1399 (2013.01); H01M 4/364 (2013.01); H01M 4/382 (2013.01); H01M 4/386 (2013.01); H01M 10/0525 (2013.01); H01M 10/0562 (2013.01);
Abstract

An interfacial additive layer for decreasing the interfacial resistance/impedance of a silicon based electrode-containing device such as, for example, an energy storage device or a micro-resistor, is disclosed. The interfacial additive layer, which is composed of a molten lithium containing salt, is formed between a silicon based electrode and a solid polymer electrolyte layer of the device. The presence of such an interfacial additive layer increases the ion and electron mobile dependent performances at the silicon based electrode interface due to significant decrease in the resistance/impedance that is observed at the respective interface as well as the impedance observed in the bulk of the device.


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