The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 19, 2022

Filed:

Feb. 25, 2020
Applicant:

Alpha and Omega Semiconductor (Cayman), Ltd., Grand Cayman, KY;

Inventors:

Xiaotian Zhang, San Jose, CA (US);

Mary Jane R. Alin, Shanghai, CN;

Bo Chen, Shanghai, CN;

David Brian Oraboni, Jr., San Jose, CA (US);

Long-Ching Wang, Cupertino, CA (US);

Jian Yin, San Ramon, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 23/31 (2006.01); H01L 25/16 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49575 (2013.01); H01L 23/3107 (2013.01); H01L 23/4952 (2013.01); H01L 23/49503 (2013.01); H01L 23/49562 (2013.01); H01L 24/48 (2013.01); H01L 25/16 (2013.01); H01L 2224/48245 (2013.01); H01L 2924/1205 (2013.01); H01L 2924/1206 (2013.01); H01L 2924/1207 (2013.01); H01L 2924/13091 (2013.01);
Abstract

A power semiconductor package comprises a lead frame, a low side field-effect transistor (FET), a high side FET, a capacitor, a resistor, an inductor assembly, a first plurality of bonding wires, and a molding encapsulation. In one example, an entirety of the inductor assembly is disposed at a position higher than an entirety of the low side FET, higher than an entirety of the high side FET, and higher than an entirety of the first plurality of bonding wires. In another example, a bottom surface of the low side FET and a bottom surface of the inductor assembly are co-planar.


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