The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 19, 2022
Filed:
Jul. 09, 2019
Applicant:
Bar-ilan University, Ramat-Gan, IL;
Inventors:
Robert Giterman, Beer-Sheva, IL;
Adam Teman, Tel-Mond, IL;
Assignee:
Bar-Ilan University, Ramat-Gan, IL;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); G11C 11/404 (2006.01); G11C 11/4091 (2006.01); G11C 11/4096 (2006.01);
U.S. Cl.
CPC ...
G11C 11/404 (2013.01); G11C 11/4091 (2013.01); G11C 11/4096 (2013.01); G11C 2211/4016 (2013.01);
Abstract
An FD-SOI GC-edRAM gain cell includes: The FD-SOI transistors are interconnected to form a storage node for retaining a data signal. The bodies of at least two of the transistors are coupled in a single well to a body voltage terminal. The write trigger signal triggers writing an input data signal from the write bit line terminal to the storage node and the read trigger signal triggers outputting the retained data signal from the storage node to the read bit line terminal.