The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 19, 2022

Filed:

Jan. 14, 2021
Applicant:

University of Florida Research Foundation, Incorporated, Gainesville, FL (US);

Inventors:

Navid Asadi-Zanjani, Gainesville, FL (US);

Mark M. Tehranipoor, Gainesville, FL (US);

Mukhil Azhagan Mallaiyan Sathiaseelan, Gainesville, FL (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06T 7/00 (2017.01); G06T 7/10 (2017.01); G06T 7/136 (2017.01); G06T 7/194 (2017.01); G06T 7/254 (2017.01); G06T 7/50 (2017.01);
U.S. Cl.
CPC ...
G06T 7/0004 (2013.01); G06T 7/10 (2017.01); G06T 7/136 (2017.01); G06T 7/194 (2017.01); G06T 7/254 (2017.01); G06T 7/50 (2017.01); G06T 2207/20036 (2013.01); G06T 2207/30141 (2013.01);
Abstract

There is a need for more effective and efficient printed circuit board (PCB) design. This need can be addressed by, for example, solutions for performing automated PCB component estimation. In one example, a method includes identifying a PCB image of a PCB; performing chromaticity-based background subtraction on the PCB image to generate a background-subtracted PCB image; performing morphological noise removal on the background-subtracted PCB image to generate a noise-removed PCB image; and performing object localization on the noise-removed PCB image to identify one or more PCB component estimations within the noise-removed PCB image.


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