The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 19, 2022
Filed:
Jun. 08, 2020
Stephen Melvin, Vancouver, CA;
Shadi Assadikhomami, Vancouver, CA;
Tor Aamodt, Vancouver, CA;
Other;
Abstract
An architecture for a Field Programmable Gate Array (FPGA) that better supports the designs of finite state machines (FSMs) generated by High-Level Synthesis (HLS) tools. The architecture is based on categorizing states of a FSM into branch free path states and independent states. A memory unit stores next state information for independent states and an accumulator unit computes next state information for branch free path states. A control unit selects the next state based on either the memory unit or the accumulator unit. An input sequence encoder encodes external inputs and current state values into encoded sequence signals that are input to the memory unit. Also disclosed is a state assignment algorithm that assigns state values to states of the FSM by first identifying branch free paths that terminate on the same state and then eliminating overlap between paths. States along the same branch free path are assigned sequential values.