The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 19, 2022

Filed:

Nov. 26, 2018
Applicants:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Ati Technologies Ulc, Markham, CA;

Inventors:

Anthony Asaro, Markham, CA;

Richard E. George, Santa Clara, CA (US);

Assignees:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

ATI TECHNOLOGIES ULC, Markham, CA;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/07 (2006.01); G06F 11/36 (2006.01); G06F 9/30 (2018.01); G06F 12/1009 (2016.01);
U.S. Cl.
CPC ...
G06F 12/1009 (2013.01); G06F 9/30101 (2013.01); G06F 11/0721 (2013.01); G06F 11/0751 (2013.01); G06F 11/0772 (2013.01); G06F 11/0778 (2013.01); G06F 11/362 (2013.01); G06F 2212/1044 (2013.01); G06F 2212/657 (2013.01);
Abstract

For one or more stages of execution of a software application at a first processor, a remap vector of a second processor is reconfigured to represent a dynamic mapping of virtual address groups to physical address groups for that stage. Each bit position of the remap vector is configured to store a value indicating whether a corresponding virtual address group is actively mapped to a corresponding physical address group. Address translation operations issued during a stage of execution of the software application are selectively processed based on the configuration of the remap vector for that stage, with the particular value at the bit position of the remap vector associated with the corresponding virtual address group controlling whether processing of the address translation operation is continued to obtain a virtual-to-physical address translation sought by the address translation operation or processing of the address translation operation is ceased and a fault is issued.


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