The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 12, 2022

Filed:

Mar. 07, 2019
Applicant:

Sumitomo Electric Industries, Ltd., Osaka, JP;

Inventors:

Shoichiro Sakai, Osaka, JP;

Eiko Imazaki, Osaka, JP;

Koji Nitta, Osaka, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B32B 3/00 (2006.01); H05K 3/38 (2006.01); C25D 3/38 (2006.01); C25D 5/02 (2006.01); C25D 5/34 (2006.01); C25D 21/12 (2006.01); H05K 3/18 (2006.01); H05K 1/09 (2006.01);
U.S. Cl.
CPC ...
H05K 3/38 (2013.01); C25D 3/38 (2013.01); C25D 5/02 (2013.01); C25D 5/34 (2013.01); C25D 21/12 (2013.01); H05K 1/09 (2013.01); H05K 3/181 (2013.01);
Abstract

A printed circuit board according to an embodiment of the present disclosure includes a base film having an insulating property, and a conductive pattern that is stacked on at least one surface of the base film and that includes a plurality of wiring parts arranged in parallel. The plurality of wiring parts have an average width of 5 μm or more and 15 μm or less. The plurality of wiring parts have an electroless plating layer and an electroplating layer stacked on the electroless plating layer. A void density at an interface between the electroless plating layer and the electroplating layer in a section of the plurality of wiring parts in a thickness direction is 0.01 μm/μm or less.


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