The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 12, 2022

Filed:

Jul. 10, 2018
Applicant:

Fungible, Inc., Santa Clara, CA (US);

Inventors:

Pradeep Sindhu, Los Altos Hills, CA (US);

Jean-Marc Frailong, Los Altos Hills, CA (US);

Bertrand Serlet, Palo Alto, CA (US);

Wael Noureddine, Santa Clara, CA (US);

Felix A. Marti, San Francisco, CA (US);

Deepak Goel, San Jose, CA (US);

Rajan Goyal, Saratoga, CA (US);

Assignee:

Fungible, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/12 (2006.01); H04L 12/46 (2006.01); G06F 13/16 (2006.01); G06F 13/42 (2006.01); G06F 12/0817 (2016.01); H04L 49/253 (2022.01); H04L 49/10 (2022.01); H04L 12/54 (2022.01); H04L 45/02 (2022.01); G06F 12/0811 (2016.01); H04L 12/70 (2013.01);
U.S. Cl.
CPC ...
H04L 12/4633 (2013.01); G06F 12/0817 (2013.01); G06F 13/1668 (2013.01); G06F 13/4282 (2013.01); H04L 12/56 (2013.01); H04L 45/02 (2013.01); H04L 49/10 (2013.01); H04L 49/253 (2013.01); G06F 12/0811 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/152 (2013.01); G06F 2213/0026 (2013.01); H04L 2012/5619 (2013.01); H04L 2012/5681 (2013.01);
Abstract

A new processing architecture is described in which a data processing unit (DPU) is utilized within a device. Unlike conventional compute models that are centered around a central processing unit (CPU), example implementations described herein leverage a DPU that is specially designed and optimized for a data-centric computing model in which the data processing tasks are centered around, and the primary responsibility of, the DPU. For example, various data processing tasks, such as networking, security, and storage, as well as related work acceleration, distribution and scheduling, and other such tasks are the domain of the DPU. The DPU may be viewed as a highly programmable, high-performance input/output (I/O) and data-processing hub designed to aggregate and process network and storage I/O to and from multiple other components and/or devices. This frees resources of the CPU, if present, for computing-intensive tasks.


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