The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 12, 2022
Filed:
Oct. 08, 2014
Applicant:
Nippon Telegraph and Telephone Corporation, Tokyo, JP;
Inventors:
Yoshihide Tonomura, Yokosuka, JP;
Daisuke Shirai, Yokosuka, JP;
Tatsuya Fujii, Yokosuka, JP;
Takayuki Nakachi, Yokosuka, JP;
Takahiro Yamaguchi, Yokosuka, JP;
Masahiko Kitamura, Yokosuka, JP;
Assignee:
NIPPON TELEGRAPH AND TELEPHONE CORPORATION, Tokyo, JP;
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 16/00 (2019.01); H03M 13/00 (2006.01); G06F 16/901 (2019.01); H03M 13/03 (2006.01); H03M 13/11 (2006.01); H03M 13/37 (2006.01);
U.S. Cl.
CPC ...
H03M 13/615 (2013.01); G06F 16/9024 (2019.01); H03M 13/036 (2013.01); H03M 13/1102 (2013.01); H03M 13/118 (2013.01); H03M 13/1191 (2013.01); H03M 13/373 (2013.01); H03M 13/3761 (2013.01); H03M 13/6393 (2013.01);
Abstract
A selective PEG algorithm, creating a sparse matrix while maintaining row weight/column weight at arbitrary multi-levels, and in the process, inactivating an arbitrary edge so that a minimum loop formed between arbitrary nodes is enlarged or performing constrained interleaving, so that encoding efficiency in the case where a matrix space is narrow is improved.