The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 12, 2022

Filed:

Oct. 20, 2020
Applicant:

Realtek Semiconductor Corp., HsinChu, TW;

Inventors:

Yu-Che Yang, Taipei, TW;

Ka-Un Chan, Hsinchu County, TW;

Yong-Ru Lu, Taipei, TW;

Shen-Iuan Liu, Taipei, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/087 (2006.01); H03L 7/091 (2006.01); H03L 7/093 (2006.01); H03L 7/10 (2006.01); H03L 7/081 (2006.01); H03L 7/099 (2006.01);
U.S. Cl.
CPC ...
H03L 7/093 (2013.01); H03L 7/0814 (2013.01); H03L 7/0991 (2013.01); H03L 7/105 (2013.01);
Abstract

The present invention provides a sub-sampling PLL including a first phase detector, a first charge pump, an oscillator and a first buffer is disclosed. In the operations of the sub-sampling PLL, the first phase detector uses a reference clock signal to sample a feedback signal to generate a first phase detection result, the first charge pump generates a first signal according to the first phase detection result and a pulse signal, the oscillator generates an output clock signal according to the first signal, and the first buffer receives the output clock signal to generate the feedback signal, and buffer further using a slew rate control signal to control a slew rate of the feedback signal.


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