The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 12, 2022
Filed:
Apr. 21, 2020
Applicant:
Renesas Electronics Corporation, Tokyo, JP;
Inventor:
Tatsuyoshi Mihara, Tokyo, JP;
Assignee:
RENESAS ELECTRONICS CORPORATION, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 21/306 (2006.01); H01L 21/762 (2006.01); H01L 27/11568 (2017.01); H01L 29/08 (2006.01); H01L 21/28 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/792 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 27/11573 (2017.01);
U.S. Cl.
CPC ...
H01L 29/42344 (2013.01); H01L 21/30604 (2013.01); H01L 21/76224 (2013.01); H01L 27/11568 (2013.01); H01L 29/0847 (2013.01); H01L 29/40117 (2019.08); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/66833 (2013.01); H01L 29/7851 (2013.01); H01L 29/792 (2013.01);
Abstract
In order to improve the reliability of a semiconductor device, in a memory cell of a split-gate type MONOS memory formed on a fin, a drain region is formed in an epitaxial layer on the fin, and a source region is formed in the fin, and a silicide layer is formed on an upper surface of the fin in which the source region is formed.