The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 12, 2022

Filed:

May. 11, 2018
Applicant:

Sharp Kabushiki Kaisha, Sakai, JP;

Inventors:

Kengo Hara, Sakai, JP;

Tohru Daitoh, Sakai, JP;

Hajime Imai, Sakai, JP;

Tetsuo Kikuchi, Sakai, JP;

Hideki Kitagawa, Sakai, JP;

Teruyuki Ueda, Sakai, JP;

Masahiko Suzuki, Sakai, JP;

Setsuji Nishimiya, Sakai, JP;

Toshikatsu Itoh, Sakai, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); G02F 1/1362 (2006.01); G02F 1/1368 (2006.01); G02F 1/1343 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1225 (2013.01); G02F 1/1368 (2013.01); G02F 1/136286 (2013.01); H01L 27/124 (2013.01); H01L 27/127 (2013.01); H01L 27/1288 (2013.01); G02F 1/13685 (2021.01); G02F 1/134363 (2013.01); G02F 1/136295 (2021.01); G02F 2201/40 (2013.01);
Abstract

Each of pixel regions of an active matrix substrate () includes: a lower insulating layer (); an oxide semiconductor layer () that is arranged on the lower insulating layer and includes an active region () of an oxide semiconductor TFT; an upper insulating layer () that is arranged on a portion of the oxide semiconductor layer so as not to be in contact with the lower insulating layer; an upper gate layer () that is arranged on the upper insulating layer and includes an upper gate electrode () and one of a plurality of gate bus lines (GL); and a source electrode and a drain electrode, wherein: the oxide semiconductor layerfurther includes an extension region () that extends from the active region () in a direction x different from a channel length direction y of the oxide semiconductor TFT as seen from a normal direction to the substrate; and the extension region () is arranged on the substrate side of one of the plurality of gate bus lines (GL) with an upper insulating layer () interposed therebetween, and includes a portion that extends so as to overlap with the one of the plurality of gate bus lines.


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