The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 12, 2022

Filed:

Jun. 30, 2020
Applicant:

Western Digital Technologies, Inc., San Jose, CA (US);

Inventors:

John Thomas Contreras, Palo Alto, CA (US);

Sayed Mobin, San Jose, CA (US);

Daniel Oh, San Jose, CA (US);

Rehan Ahmed Zakai, San Ramon, CA (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/00 (2006.01); H05K 1/02 (2006.01); H05K 1/11 (2006.01); H05K 1/14 (2006.01); H05K 3/46 (2006.01); H01L 23/66 (2006.01); H01L 23/538 (2006.01); H01L 25/18 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5386 (2013.01); H01L 23/5383 (2013.01); H01L 23/66 (2013.01); H01L 24/48 (2013.01); H01L 25/18 (2013.01); H01L 2224/48145 (2013.01); H01L 2224/48227 (2013.01);
Abstract

A circuit interconnect for high bandwidth and high die-count memory stacks. The circuit interconnect may include a first ground trace, a first signal trace, a second ground trace, and a second signal trace. The first ground trace may reside in a first layer of a multilayer printed circuit board. The first signal trace may be positioned adjacent to the first ground trace within the first layer. The second ground trace may reside within a second layer of the multilayer printed circuit board. The second signal trace may be positioned adjacent to the second ground trace within the second layer.


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