Row address comparator for a row redundancy control circuit in a memory

Abstract

Disclosed is a row address comparator with voltage level shifting and latching functionality and including: an evaluation section for comparing two row addresses in a first voltage domain and outputting an initial match signal in a second voltage domain; and a latch section for outputting a latched final match signal based on the initial match signal. The comparator employs a first clock signal (CLK), a second clock signal (CLK) that is different from CLKand a third clock signal (CLK) that is inverted with respect to CLK. CLKsandcontrol pre-charge and evaluation operations within the evaluation section with CLKbeing set to minimize hold time. CLKsandcontrol the latch operation within the latch section. Feedback loops in both sections enhance performance. Also disclosed are a control circuit that incorporates the comparator and a method for implementing row redundancy in a memory.