The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 12, 2022

Filed:

Aug. 29, 2016
Applicant:

Tianjin University, Tianjin, CN;

Inventors:

Hongjie Jia, Tianjin, CN;

Chaoyu Dong, Tianjin, CN;

Yilang Jiang, Tianjin, CN;

Tao Jiang, Tianjin, CN;

Lei Wang, Tianjin, CN;

Assignee:

TIANJIN UNIVERSITY, Tianjin, CN;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/20 (2020.01); H02J 13/00 (2006.01); G01R 21/133 (2006.01); G06F 17/16 (2006.01); G06F 119/06 (2020.01); G06F 111/10 (2020.01); G06F 119/12 (2020.01);
U.S. Cl.
CPC ...
G06F 30/20 (2020.01); G01R 21/133 (2013.01); G06F 17/16 (2013.01); H02J 13/00002 (2020.01); G06F 2111/10 (2020.01); G06F 2119/06 (2020.01); G06F 2119/12 (2020.01); H02J 2203/20 (2020.01);
Abstract

The present disclosure discloses a method for fast determining a time-delay stability margin of a power system, which focuses on three steps, i.e., Jordan standardization, Taylor separation and Schur simplification, to reconstruct a new time delay system and reduce the system dimension. In this method, firstly, a time delay model is Jordan standardized; further, Taylor expansion is applied in a process for separating state variables with time delay from stage variables without time delay; then, balanced model reduction is realized by Schur simplification; and finally, a WSCC 3-generator-9-bus power system with multiple delays will be used to validate the proposed method via several typical criteria.


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