The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 12, 2022

Filed:

Jul. 31, 2019
Applicant:

21, Inc., San Francisco, CA (US);

Inventors:

Veerbhan Kheterpal, San Francisco, CA (US);

Daniel Firu, San Francisco, CA (US);

Nigel Drego, San Francisco, CA (US);

Assignee:

21, Inc., San Francisco, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 16/2458 (2019.01); G06Q 20/06 (2012.01); G06F 16/951 (2019.01); G06Q 20/36 (2012.01); G06Q 20/38 (2012.01); G06Q 40/04 (2012.01); H04L 9/06 (2006.01); H04L 9/32 (2006.01);
U.S. Cl.
CPC ...
G06F 16/2465 (2019.01); G06F 16/951 (2019.01); G06Q 20/06 (2013.01); G06Q 20/3678 (2013.01); G06Q 20/3827 (2013.01); G06Q 40/04 (2013.01); H04L 9/0643 (2013.01); H04L 9/3236 (2013.01); H04L 2209/30 (2013.01); H04L 2209/38 (2013.01);
Abstract

An integrated circuit may be provided with cryptocurrency mining capabilities. The integrated circuit may include control circuitry and a number of processing cores that complete a Secure Hash Algorithm 256 (SHA-256) function in parallel. Logic circuitry may be shared between multiple processing cores. Each processing core may perform sequential rounds of cryptographic hashing operations based on a hash input and message word inputs. The control circuitry may control the processing cores to complete the SHA-256 function over different search spaces. The shared logic circuitry may perform a subset of the sequential rounds for multiple processing cores. If desired, the shared logic circuitry may generate message word inputs for some of the sequential rounds across multiple processing cores. By sharing logic circuitry across cores, chip area consumption and power efficiency may be improved relative to scenarios where the cores are formed using only dedicated logic.


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