The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 12, 2022

Filed:

Dec. 04, 2020
Applicant:

Neuroblade, Ltd., Tel Aviv-Jaffa, IL;

Inventors:

Elad Sity, Kfar Saba, IL;

Eliad Hillel, Kfar Saba, IL;

Assignee:

NeuroBlade Ltd., Tel Aviv, IL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/16 (2006.01); G06F 9/30 (2018.01); G06F 11/16 (2006.01); G06F 9/38 (2018.01); G06F 15/80 (2006.01); G11C 7/10 (2006.01); G11C 11/4076 (2006.01); G11C 11/408 (2006.01); G06N 3/04 (2006.01); G06F 11/10 (2006.01); G11C 11/4093 (2006.01); G06F 13/16 (2006.01); G06F 15/76 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1658 (2013.01); G06F 9/3001 (2013.01); G06F 9/3885 (2013.01); G06F 9/3889 (2013.01); G06F 9/3895 (2013.01); G06F 11/102 (2013.01); G06F 11/1016 (2013.01); G06F 11/16 (2013.01); G06F 11/1616 (2013.01); G06F 13/1657 (2013.01); G06F 15/8038 (2013.01); G06N 3/04 (2013.01); G11C 7/1072 (2013.01); G11C 11/1655 (2013.01); G11C 11/1657 (2013.01); G11C 11/1675 (2013.01); G11C 11/408 (2013.01); G11C 11/4076 (2013.01); G11C 11/4093 (2013.01); G06F 2015/765 (2013.01);
Abstract

Distributed processors and methods for compiling code for execution by distributed processors are disclosed. In one implementation, a distributed processor may include a substrate; a memory array disposed on the substrate; and a processing array disposed on the substrate. The memory array may include a plurality of discrete memory banks, and the processing array may include a plurality of processor subunits, each one of the processor subunits being associated with a corresponding, dedicated one of the plurality of discrete memory banks. The distributed processor may further include a first plurality of buses, each connecting one of the plurality of processor subunits to its corresponding, dedicated memory bank, and a second plurality of buses, each connecting one of the plurality of processor subunits to another of the plurality of processor subunits.


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