The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 12, 2022

Filed:

May. 23, 2019
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Shail Aditya Gupta, San Jose, CA (US);

Rishi Surendran, San Jose, CA (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/46 (2006.01); G06F 9/50 (2006.01); G06F 16/901 (2019.01); G06F 13/28 (2006.01);
U.S. Cl.
CPC ...
G06F 9/5005 (2013.01); G06F 13/28 (2013.01); G06F 16/9024 (2019.01);
Abstract

Implementing an application using a plurality of data processing engines (DPEs) can include, in a first pass, mapping, using computer hardware, a data flow graph onto an array of DPEs by minimizing direct memory access (DMA) circuit usage and memory conflicts in the array of DPEs and, in response to determining that a mapping solution generated by the first pass requires an additional DMA circuit not specified by the data flow graph, inserting, using the computer hardware, additional buffers into the data flow graph. In a second pass, the additional buffers can be mapped, using the computer hardware, onto the array of DPEs by minimizing the memory conflicts in the array of DPEs.


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