The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 12, 2022
Filed:
Jun. 09, 2020
Applicants:
Verisilicon Microelectronics (Shanghai) Co., Ltd., Shanghai, CN;
Verisilicon Holdings Co., Ltd., George Town, KY;
Assignees:
VeriSilicon Microelectronics (Shanghai) Co., Ltd., Shanghai, CN;
VeriSilicon Holdings Co., Ltd., George Town, KY;
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/523 (2006.01); G06F 7/544 (2006.01); G06F 7/50 (2006.01);
U.S. Cl.
CPC ...
G06F 7/5443 (2013.01); G06F 7/50 (2013.01); G06F 7/523 (2013.01);
Abstract
A circuit for performing multiply/accumulate operations evaluates a type of each value of a pair of input values. Signed values are split into sign and magnitude. One or more pairs of arguments are input to a multiplier such that the arguments have fewer bits than the magnitude of signed values or unsigned values. This may include splitting input values into multiple arguments and inputting multiple pairs of arguments to the multiplier for a single pair of input values.