The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 12, 2022

Filed:

May. 22, 2018
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Layne A. Berge, Rochester, MN (US);

Matthew S. Doyle, Chatfield, MN (US);

Manuel Orozco, Rochester, MN (US);

John R. Dangler, Rochester, MN (US);

Thomas W. Liang, Rochester, MN (US);

Jason J. Bjorgaard, Rochester, MN (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01); H05K 1/18 (2006.01); H05K 1/02 (2006.01); H05K 1/16 (2006.01);
U.S. Cl.
CPC ...
G01R 31/2818 (2013.01); G01R 31/2813 (2013.01); H05K 1/0268 (2013.01); H05K 1/165 (2013.01); H05K 1/181 (2013.01);
Abstract

The present disclosure describes printed circuit board performance evaluation techniques. In some cases, a printed circuit board performance evaluation process may include determining a first set of electrical properties associated with an interface between components of a printed circuit board, where the interface is disposed on an internal or external layer of the printed circuit board. After selective application of a sheet of dielectric material to a portion of a transmission line in the interface, a second set of electrical properties associated with the interface may be determined. The first set of electrical properties may be compared to the second set of electrical properties to evaluate printed circuit board performance. In other cases, the interface may include a trace inductor, and electrical properties of the interface before and after application of a ferrous material may be compared to evaluate printed circuit board performance.


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