The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 12, 2022

Filed:

May. 07, 2020
Applicant:

Cirrus Logic International Semiconductor Ltd., Edinburgh, GB;

Inventors:

Rkia Achehboune, Edinburgh, GB;

Roberto Brioschi, Austin, TX (US);

Dimitris Drogoudis, Edinburgh, GB;

David Patten, Austin, TX (US);

Assignee:

Cirrus Logic, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04R 19/00 (2006.01); B81B 7/00 (2006.01); B81C 1/00 (2006.01); H04R 19/04 (2006.01); H04R 31/00 (2006.01);
U.S. Cl.
CPC ...
B81B 7/0064 (2013.01); B81C 1/00269 (2013.01); H04R 19/04 (2013.01); H04R 31/00 (2013.01); B81B 2201/0257 (2013.01); B81B 2203/0127 (2013.01); B81B 2207/012 (2013.01); H04R 2201/003 (2013.01);
Abstract

The Application describes a substrate design for a MEMS transducer package. The substrate is defined by a conductive layer which forms the upper and lower surfaces of the substrate. The substrate is also provided with a conductive portion which is electrically isolated from the rest of the conductive layer. The conductive portion is supported between a first plane defined by the upper surface of the substrate and a second plane defined by the lower surface of the substrate by an electrically insulating moulding substance.


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