The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 05, 2022

Filed:

Jun. 16, 2021
Applicant:

Purdue Research Foundation, West Lafayette, IN (US);

Inventors:

Niharika Thakuria, West Lafayette, IN (US);

Sumeet Kumar Gupta, West Lafayette, IN (US);

Assignee:

Purdue Research Foundation, West Lafayette, IN (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/22 (2006.01); H01L 29/78 (2006.01); H01L 29/76 (2006.01); H01L 27/1159 (2017.01); H01L 29/24 (2006.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78391 (2014.09); G11C 11/223 (2013.01); G11C 11/2273 (2013.01); G11C 11/2275 (2013.01); H01L 27/1159 (2013.01); H01L 29/24 (2013.01); H01L 29/516 (2013.01); H01L 29/7606 (2013.01);
Abstract

A polarization induced strain coupled two dimensional field effect transistor (PoSt FET) memory cell is disclosed which includes a transistor including a source contact, a drain contact, a gate contact, a back contact, a channel disposed atop the gate contact, wherein the channel and the gate are separated by an electrically insulating material, and a piezoelectric (PE)/ferroelectric(FE) (PE/FE) layer disposed between the gate contact and the back contact and configured to store bit information in form of ferroelectric polarization (P), wherein a ratio of cross-sectional area of the channel to cross-sectional area of the PE/FE layer is between about 0.03 to about 0.07.


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