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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11296088 B1

PDFFull Text
Date of Patent:
Apr. 05, 2022

Filed:

Jul. 24, 2019

Semiconductor device including air gaps and method for fabricating the same

Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventors:

Chang-Youn Hwang, Gyeonggi-do, KR;

Noh-Jung Kwak, Gyeonggi-do, KR;

Hong-Gu Yi, Gyeonggi-do, KR;

Yun-Je Choi, Gyeonggi-do, KR;

Se-Han Kwon, Gyeonggi-do, KR;

Ki-Soo Choi, Gyeonggi-do, KR;

Seung-Bum Kim, Gyeonggi-do, KR;

Do-Hyung Kim, Gyeonggi-do, KR;

Doo-Sung Jung, Gyeonggi-do, KR;

Dae-Sik Park, Gyeonggi-do, KR;

Assignee:

SK hynix Inc., Gyeonggi-do, KR;

Attorney:

IP & T Group LLP

Primary Examiner:

Aaron J Gray

Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 21/768 (2006.01); H01L 21/764 (2006.01); H01L 21/3213 (2006.01); H01L 27/24 (2006.01); H01L 45/00 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/535 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10805 (2013.01); H01L 21/32139 (2013.01); H01L 21/764 (2013.01); H01L 21/7682 (2013.01); H01L 21/76831 (2013.01); H01L 21/76832 (2013.01); H01L 21/76897 (2013.01); H01L 23/528 (2013.01); H01L 23/5223 (2013.01); H01L 23/5226 (2013.01); H01L 23/535 (2013.01); H01L 27/10814 (2013.01); H01L 27/10823 (2013.01); H01L 27/10855 (2013.01); H01L 27/10876 (2013.01); H01L 27/10888 (2013.01); H01L 27/2436 (2013.01); H01L 27/2463 (2013.01); H01L 45/06 (2013.01); H01L 45/16 (2013.01);
Abstract

Disclosed are a semiconductor device capable of reducing parasitic capacitance between adjacent conductive structures and a method for fabricating the same. The semiconductor device includes a plurality of bit line structures each comprising a first contact plug formed over a substrate and a bit line formed over the first contact plug. A spacer structure having air gaps is formed on sidewalls of the first contact plug and on sidewalls of the bit line. An plug isolation layer is formed between the plurality of bit line structures. The isolation layer includes an opening. A second contact plug is formed in the opening and a memory element is formed over the second contact plug.

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