The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 05, 2022
Filed:
Jun. 18, 2020
Applicant:
Socionext Inc., Kanagawa, JP;
Inventor:
Isaya Sobue, Yokohama, JP;
Assignee:
SOCIONEXT INC., Kanagawa, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/02 (2006.01); H01L 21/8234 (2006.01); H01L 21/02 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01); B82Y 10/00 (2011.01);
U.S. Cl.
CPC ...
H01L 21/823487 (2013.01); H01L 21/02603 (2013.01); H01L 27/0207 (2013.01); H01L 27/092 (2013.01); H01L 29/0676 (2013.01); H01L 29/42312 (2013.01); H01L 29/7827 (2013.01); B82Y 10/00 (2013.01);
Abstract
A layout structure of an output circuit using vertical nanowire (VNW) FETs is provided. The output circuit includes a transistor of a first conductivity type provided between a power supply and an output signal line and configured to receive an output control signal at its gate. The transistor includes a plurality of VNW FETs placed in an array in the X and Y directions, and the plurality of VNW FETs have tops connected to the output signal line, bottoms to which a power supply voltage is supplied, and gates to which the output control signal is supplied.