The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 05, 2022

Filed:

Sep. 23, 2020
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Dong Jin Shin, Hwaseong-si, KR;

Ji Su Kim, Seoul, KR;

Dae Seok Byeon, Seongnam-si, KR;

Ji Sang Lee, Iksan-si, KR;

Jun Jin Kong, Yongin-si, KR;

Eun Chu Oh, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 16/26 (2006.01); G11C 16/10 (2006.01); G11C 5/14 (2006.01); G11C 16/08 (2006.01); G11C 16/32 (2006.01); G11C 11/56 (2006.01); G11C 16/24 (2006.01);
U.S. Cl.
CPC ...
G11C 16/26 (2013.01); G11C 5/147 (2013.01); G11C 11/5642 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/24 (2013.01); G11C 16/32 (2013.01); G11C 2211/5642 (2013.01);
Abstract

A storage device including, a plurality of non-volatile memories configured to include a memory cell region including at least one first metal pad; and a peripheral circuit region including at least one second metal pad and vertically connected to the memory cell region by the at least one first metal pad and the at least one second metal pad, and a controller connected to the plurality of non-volatile memories through a plurality of channels and configured to control the plurality of non-volatile memories, wherein the controller selects one of a first read operation mode and a second read operation mode and transfers a read command corresponding to the selected read operation mode to the plurality of non-volatile memories, wherein one sensing operation is performed to identify one program state among program sates in the first read operation mode, and wherein at least two sensing operations are performed to identify the one program state among the program states in the second read operation mode.


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