The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 05, 2022
Filed:
Jul. 27, 2020
Boe Technology Group Co., Ltd., Beijing, CN;
Junrui Zhang, Beijing, CN;
Xuehui Zhu, Beijing, CN;
Lijia Zhou, Beijing, CN;
Zhidong Wang, Beijing, CN;
Quanguo Zhou, Beijing, CN;
Yungchiang Lee, Beijing, CN;
Meng Guo, Beijing, CN;
Jiuyang Cheng, Beijing, CN;
Zongze He, Beijing, CN;
Qin Liu, Beijing, CN;
BOE TECHNOLOGY GROUP CO., LTD., Beijing, CN;
Abstract
Counter, pixel circuit, display panel, display device are provided. The counter includes: start-up circuit generating and outputting start-up signal by clock signal; M first and M second combinational logic circuits, alternate and cascaded, where M is integer no less than 1. Input terminal of first combinational logic circuit is coupled to output terminal of start-up circuit or second combinational logic circuit of previous stage, input terminal of second combinational logic circuit is coupled to output terminal of first combinational logic circuit of previous stage. Clock signal terminals of first, second combinational logic circuits are for inputting clock signal. First combinational logic circuit is for outputting clock signal in first time period and continuously outputting low level signal in second time period. Second combinational logic circuit is for outputting inverted signal of clock signal in third time period and continuously outputting low level signal in fourth time period.