The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 05, 2022

Filed:

Mar. 25, 2019
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Naman Gupta, Faridabad, IN;

Rajat Chauhan, Bangalore, IN;

Santhosh Kumar Srinivasan, Bengaluru, IN;

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 19/165 (2006.01); G01R 31/382 (2019.01); G05F 3/26 (2006.01); H03K 3/037 (2006.01);
U.S. Cl.
CPC ...
G01R 19/16519 (2013.01); G01R 19/16523 (2013.01); G01R 31/382 (2019.01); G05F 3/262 (2013.01); H03K 3/0377 (2013.01);
Abstract

Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a Zener diode, a first current source, a first n-type field effect transistor (FET), a first inverter circuit, and a second current source. The Zener diode has a cathode coupled to a first node and an anode coupled to a second node. The first current source has a first terminal coupled to the second node and a second terminal coupled to a ground terminal. The first n-type FET has a gate terminal coupled to the second node, a source terminal coupled to the ground terminal, and a drain terminal coupled to a third node. The first inverter circuit has an input coupled to the third node and an output coupled to a fourth node. The second current source has a first terminal coupled to a fifth node and a second terminal coupled to the third node.


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