The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 29, 2022

Filed:

Jun. 03, 2021
Applicant:

Sambanova Systems, Inc., Palo Alto, CA (US);

Inventors:

Fahim ur Rahman, Sunnyvale, CA (US);

Sang-Min Lee, Palo Alto, CA (US);

Jin-Uk Shin, San Jose, CA (US);

Assignee:

SAMBANOVA SYSTEMS, INC., Palo Alto, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/07 (2006.01); H03L 7/081 (2006.01); G06F 1/04 (2006.01); H03K 5/135 (2006.01);
U.S. Cl.
CPC ...
H03L 7/07 (2013.01); G06F 1/04 (2013.01); H03K 5/135 (2013.01); H03L 7/0814 (2013.01);
Abstract

A clock stretcher includes a digital DLL that derives delayed versions of an input clock signal, and a combiner that cyclically selects the delayed versions to generate a modified clock signal. The combiner uses a hop code, dependent on a sensed condition, to determine the step size for the cyclical selection. The digital DLL corrects its delay speed at discrete times, during which it may be active. If the DLL delay line becomes slower while it is active, the modified clock signal would incur a glitch. The clock stretcher corrects for this glitch by using an increased hop code when a speed change occurs. The clock stretcher may operate from a sensed power supply without intervening voltage regulation.


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